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  • eBook:ASIC Design and Synthesis

    ASIC Design and Synthesis

    RTL Design Using Verilog
    Vaibbhav Taraate
    978-981-33-4642-0
    2021
    Edition 1
    • Unique to interpretation of ASIC design using Verilog
    • Practical ASIC design scenarios and issues and helpful to professionals
    • More than 150 practical examples for ASIC design, Synthesis and timing analysis
    • Key case studies in the generic form and design synthesis and timing closure for ASIC

    €260

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