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  • Victor Champac; Jose Garcia Gervacio
    978-3-319-75465-9
    2018
    Edition 1
    • Describes in detail the digital design of integrated circuit under process variations with a focus on design-time understanding and optimization
    • Follows a step-by-step sequence in methodology, going from logic gates to logic paths to circuit level, in order to explain the behavior of process variations at the different levels of abstraction
    • Presents novel design issues for FinFET based digital circuits
    • Provides step-by-step examples of quantitative estimation of the timing performance of logic cells and logic paths, as well as a comparison with Spice simulation results

    €220

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