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  • Pascal Meinerzhagen; Adam Teman; Robert Giterman; Noa Edri; Andreas Burg; Alexander Fish
    978-3-319-60402-2
    2018
    Edition 1
    • Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applications;
    • Models the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurements;
    • Describes various memory optimizations, including unique bitcell and assist circuits, targeted at increased retention time and reduced power consumption while hardly compromising area and speed;
    • Demonstrates several new techniques at the circuit, architectural, and algorithmic levels which enable NTV and subthreshold operation of GC-eDRAM, implementation of GC-eDRAM in aggressively scaled CMOS nodes, as well as soft-error tolerance.
    • Includes supplementary material: sn.pub/extras
    €180 €162
    10% OFF

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