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  • Eduard Cerny; Surrendra Dudani; John Havlicek; Dmitry Korchemny
    978-3-319-07139-8
    2015
    Edition 2
    • Provides a comprehensive guide to assertion-based verification with System Verilog Assertions (SVA)
    • Includes step-by-step examples of how SVA can be used to construct powerful and reusable sets of properties
    • Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 System Verilog standard

    €220

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