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  • A Textbook from Silicon Valley Polytechnic Institute
    John Michael Williams
    978-3-319-04789-8
    2014
    Edition 2
    • Covers the entire Verilog language – using most of it in practice
    • Provides 27 lab exercises, with complete and tested answers
    • Explains and emphasizes synthesizability, wherever it pertains to language features
    • Develops as a major project a synthesizable 70,000-gate Ser Des
    • Presents synthesis-relevant usage of System Verilog and the basic functionality of Verilog-AMS
    • Includes supplementary material: sn.pub/extras

    €220

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