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  • Vladislav Vashchenko; Mirko Scholz
    978-3-319-03221-4
    2014
    Edition 1
    • Provides a systematic approach to on-chip ESD protection for system-level IC pins
    • Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure
    • Includes a comprehensive description of wafer- level and component-level test methodologies
    • Includes supplementary material: sn.pub/extras

    €160

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