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Automated Analysis of Virtual Prototypes at the Electronic System Level

Design Understanding and Applications

Mehran Goli; Rolf Drechsler

978-3-030-44282-8

2020
Edition 1
- Provides an extensive introduction to the field of SystemC-based virtual prototype (VP) analysis at the electronic system level
- Describes a design understanding methodology from both debugger-based and compiler-based perspectives
- Illustrates a semi-formal verification approach to check the validity of a given VP against its specification, user-defined rules and protocol
- Discusses a security validation approach to validate the run-time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity)
- Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels
€160

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