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Designing 2D and 3D Network-on-Chip Architectures

Konstantinos Tatas; Kostas Siozios; Dimitrios Soudris; Axel Jantsch

978-1-4614-4274-5

2014
Edition 1
- Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect
- Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance
- Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management
€180 €162
10% OFF

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