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  • Sandeep Saini
    978-1-4614-1323-3
    2015
    Edition 1
    • Provides practical solutions for delay and power reduction for on-chip interconnects and buses
    • Focuses on Deep Sub micron technology devices and interconnects
    • Offers in depth analysis of delay, including details regarding crosstalk and parasitics
    • Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects
    • Provides detailed simulation results to support the theoretical discussions
    • Provides details of delay and power efficient bus coding techniques

    €180

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