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  • Methods and Tools for Verification of System-Level Designs
    Sudipta Kundu; Sorin Lerner; Rajesh K. Gupta
    978-1-4419-9359-5
    2011
    Edition 1
    • Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification
    • Uses a combination of formal techniques to do scalable verification of system designs completely automatically
    • Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL
    • Written by researchers in work in mainstream hardware and software design and includes results from both academia and industry

    €180

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