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  • Tsutomu Sasao
    978-1-4419-8104-2
    2011
    Edition 1
    • Describes in detail the synthesis of logic functions using memories
    • Includes a look-up tables (LUT) cascade as a new architecture for logic synthesis
    • Shows logic design methods for index generation functions
    • Introduces C-measure, which specifies the complexity of Boolean functions
    • Presents hash-based design methods, which efficiently synthesize index generation functions by pairs of smaller memories and can be applied to IP address tables, packet filtering, terminal access controllers, memory patch circuits, virus scanning circuits, fault map of memories, and pattern matching
    • Includes supplementary material: sn.pub/extras
    €180 €162
    10% OFF

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