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  • Zhiheng Cao; Shouli Yan
    978-1-4020-8450-8
    2008
    Edition 1
    • Implementation detail of three state-of-the-art low-power high-performance ADC and clock multiplier PLL designs using unique architectures
    • Concise and graphical explanation of key points in ADC/PLL design at both architecture and circuit level
    • Theory backed by extensive measurement results from actual silicon

    €180

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