"eBook ISBN","Title","Subtitle","Authors/editors","Copyright year","Edition","DOI","Price (EUR)","Additional info"
"978-981-15-1314-5","Logic Synthesis and SOC Prototyping","RTL Design using VHDL","Vaibbhav Taraate",2020,"1","https://doi.org/10.1007/978-981-15-1314-5",170,""